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Extra resources for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)
In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 180-186, 1990. C. F. Wong. Efficient shape curve construction in floorplan design. 5 _ - - 966 j17242 281 J 1431 2 125 1585 6782 2 15 265 265 3 11 the European Conference on Design Automation, pages 356-360, 1991. High Performance Multichip Interconnection Design D. Zhou and F. Tsui Department of Electrical Engineering The University of North Carolina at Charlotte Charlotte, NC 28223 D. S. Gao Sun Microsystems, Inc. 2550 Garcia Avenue Mountain View, CA 94043-1100 Abstract In this paper we discuss how to express the transfer function of an RLC-tree structured system in terms of moments, and derive an analytical method to calculate the moments.
09 . 11 Accuracy In choosing a delay simulator, one traditionally measures the accuracy of the available choices. ). 2 We use nets of 4 to 7 pins using three technology files, representing three different resistance ratios. Table 1 gives parameters for three interconnect technologies which we call IC1, IC2, and IC3. 8p CMOS process). 51 Table 2: Accuracy of the Elmore and Two-Pole estimators. The average ratio between "actual" SPICE delay and estimated delay is computed over 100 random nets with pin locations uniformly distributed over the layout area.
We have run trials on sets of 500 nets for each of several net sizes; pin locations were randomly chosen from a uniform distribution in a square layout region. Our inputs correspond to the same IC parameters studied in Section 3. , BBORT) and LDT constructions, and of the minimum spanning tree (MST) and shortest path tree (SPT) constructions, for the IC1 technology. 5 Delay for each tree is normalized to the ORT delay of the same net. Wirelengths are similarly compared, with the cost of each tree normalized to the MST cost of the net.
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